Switched capacitor (SC) circuit technique is widely used in analog sampled-data signal processing applications today. There are a number of advantages: (a) The switched capacitors can replace large valued resistors which are not readily integrable. (b) The ratio of capacitance can be controlled better than the ratio of resistance in integrated circuits (IC). Thus, the SC integrator has been widely used as a basic building block to replace the conventional integrator with an input resistance and a capacitance feedback around an operational amplifier in MOS ICs. However, capacitors occupy relatively large area in an IC.
Another basic building block for filter design is the differentiator. In a paper entitled: "Realization of IIR/FIR and N-path filters using novel switched-capacitor technique", published in the IEEE Transactions on Circuits and Systems, volume CAS-37, pp. 91-106, Jan. 1990, the authors T. C. Yu, C. Y. Wu and S. S. Chang described how differentiators can be used as basic building blocks for filter designs. The structures have the advantages of being simple, parasitic free and less sensitive to offset voltages and power supply voltage changes. However, the scheme uses switched capacitors, which again occupy relatively large IC areas.
There is another class of circuits known as the switched current (SI) circuit, which does not require any external capacitors. The basic circuit is shown in FIG. 1. It is a complementary pair of current mirrors. The input current and the output current of this complementary current mirror are sequentially switched.
In FIG. 1, NM and MN are n-channel MOS transistors (MOSFET). NM is connected as an MOS diode with the gate and the drain short-circuited. The input current Iin and the constant current source In are fed to the common gate and drain terminal of NM. The magnitude of In should exceed the magnitude of any possible negative Iin, so the MOS diode is never reverse biased. This common gate and drain of NM is connected to the gate of the mirroring MOSFET MN through a switch SW1. The sources of NM and MN are connected together to the negative dc power supply, say the ground. When SW1 is closed by a clock pulse .phi.1, the circuit becomes a current mirror in that the drain current of MN, IDN, mirrors the current Iin+In, as is well-known in the art.
The mirrored drain current IDN is fed to another complementary current mirror with p-type channel MOSFET PM and MP. This complementary current mirror is a dual of the n-channel MOSFET current mirror. As before, PM is connected as an MOS diode with the drain and the gate short-circuited. This common drain and gate terminal of PM is connected to the gate of the mirroring MOSFET MP through a switch SW2, which is controlled by a clock pulse .phi.2. The drain of MP is connected to a load RL. When SW2 is closed, the drain current of MP is the mirror current IDN.
In operation, .phi.1 and .phi.2 are sequentially switched and non-overlapping. When SW1 is first closed, the drain current IDN is caused to mirror the current Iin+In, and to flow into PM. When SW1 is then opened, IDN continues to flow, because the gate capacitance of MN retains the gate charge and holds the gate voltage of MN constant until SW1 is closed again. Next, when SW2 is closed, the current IDN is mirrored as IL to flow into RL. Thus, after two time steps, the output current mirrors the current Iin+In. The drain current IL continues to flow even after SW2 is opened, because the gate capacitance of MP can hold the gate charge until SW2 is closed again.
The feature of this switched current circuit is that there is no capacitor used, and the circuit, together with the switches, is composed of only MOSFETs. Therefore, the circuit can be fabricated in an IC and occupies very small area. However, up to now, the SI circuit has not been utilized in filter designs, and in particular, for filter designs based on differentiators.